Exploitability verification

Not a rating.
A proof.

If we can't exploit it, we won't call it a vulnerability. ELTON's exploitability verification does not theorize. It demonstrates, through real access to the running device, and evidences the result for regulatory review. Physical device or software-only (SaMD), the bar is the same: proof against the running product.

Theory, opinion, or proof.

Threat modelTHEORYHuman pentestVARIABLEELTON verificationPROVENEvidence traced to your own documents

Threat models predict. Human pentests vary with the tester and the week. ELTON verification is cold fact: exploited on the running device, evidenced, and traced back to your own documentation.

From threat model to test case

Test cases fall from a threat model.

The twin’s components, interfaces, data flows, and assets are threat modeled with MITRE EMB3D: component types map to properties (PIDs), properties map to threats (TIDs), and ELTON extends both where EMB3D stops. Every threat pins to a component, test cases generate against exactly that scope, and the same machinery validates a new vulnerability the day it appears.

1 · THREAT MODEL THE TWINDigital TwinComponents · InterfacesData flows · AssetsEMB3D Threat ModelComponent type → PID → TIDMITRE EMB3D baseline + ELTON PIDs and TIDsPID-21 → TID-2XXThreat InstancesEach pinned to one component/PID pairTID-207 · JTAG left enabledTID-115 · Update spoofing2 · GENERATE TEST CASESTest CasesGenerated per threat, scoped to the exact component that carries it. Same scope items drive the pentest plan.EL-1041 · UARTEL-1042 · FW SIGEL-1043 · BLEEL-1044 · API AUTHEL-1045 · FUZZDetermined on the flyA new CVE lands on the twin. ELTON derivesthe test case that proves or disproves itand queues it against the device.3 · EXECUTE, RESULT, PROMOTEExecutePentest runs and on-the-flyvalidations, in your lab orours over TestLink™.ResultPASSFAILEvery run lands with narrative,confidence, and evidence.Promote onceVULNERABILITYWEAKNESSOne finding per result, copywritten and rated by ELTONautomatically. The result stays attached as verificationevidence for this and any other finding that cites it.
Weakness vs. vulnerability

The distinction that matters.

Vulnerability

Exploitable today

Reachable from the real attack surface and substantiated by a test case generated and executed against the target. Real. Worth a developer's time.

Weakness

Latent, not exploitable today

Worth tracking, not worth interrupting a release for. It does not flood the backlog as if it were urgent, and it ships dismissed with its reasoning.

Three-tier verification

Graduated confidence, not a guess.

Every tier adds evidentiary weight. Developers only see what survives, and each dismissal is backed by the tier that cleared it.

L1 · Digital twin

~30-40% Not Affected

Reachability and control analysis against the twin removes findings that have no path before anyone touches the device.

L2 · Code & firmware

~50-65% Not Affected

Static and dynamic analysis of the actual code and firmware confirms or kills the finding at the binary level.

L3 · Real hardware

~70-85% Not Affected

On-device exploitation through TestLink™. The strongest evidence there is: an executed test case, pass or fail.

Verification, traced to the twin

FDA traceability, automated.

A finding is not closed by opinion. Every test case comes from the device’s own threat model, runs at the deepest tier you open, and lands as evidence: an unbroken chain from CVE to determination that reviewers can follow. Deeper access closes more findings as Not Affected, and every VEX statement gets stronger.

FULL REGULATORY TRACEABILITY · EVERY RESULT TRACES BACK TO THE TWINDigital TwinComponents, interfaces,data flows, assetsTest CaseEMB3D PID + LLM logic,tailored to this deviceExecuteAt the deepestavailable tierResultPASSFAIL+ evidence and narrativeFindingAffected / Not AffectedVEX OUTDEEPER ACCESS, HIGHER CONFIDENCE, MORE FINDINGS CLEAREDLEVEL 1Digital Twin MetadataArchitecture, SBOM, reachability andsecurity-profile overlay. Reason aboutexploitability from composition.CLOSED AS NOT AFFECTED30-40%Baseline confidenceLEVEL 2Code & FirmwareCustom harnesses from real code. Staticanalysis and emulation confirm which paths areactually reachable.CLOSED AS NOT AFFECTED50-65%Strong confidenceLEVEL 3Real Hardware RuntimeLive exploit attempts on the actual device.What truly works, and what does not, on realsilicon.CLOSED AS NOT AFFECTED70-85%Highest confidence
Proof over probability

Finding the 1%.
Prove the 99% don't.

Autonomous agents probe every attack surface with human-like reasoning. Findings are only accepted when exploitability is confirmed through controlled, non-destructive validation. Every verified finding leaves a traceable artifact: test case, execution log, result, and VEX status. If it can't be proven, it doesn't ship.

Bring a hard one

Hand us a finding you cannot rule out.

Start with one device. We build the twin from documentation your quality system already produces, run AI discovery remotely, and show you the graph: the handful to fix, and the evidence for everything else.

Questions

Common questions about exploitability verification.

What is exploitability verification?

Exploitability verification is a proof, not a rating. ELTON does not theorize that a finding is exploitable, it demonstrates it through real access to the running device and evidences the result for regulatory review. If it cannot be exploited, ELTON will not call it a vulnerability. The bar is the same for a physical device or software only (SaMD).

What is the difference between a weakness and a vulnerability?

A vulnerability is exploitable today: reachable from the real attack surface and substantiated by a test case generated and executed against the target. A weakness is latent. It is worth tracking, not worth interrupting a release for, and it ships dismissed with its reasoning instead of flooding the backlog as if it were urgent.

How are security test cases generated for a medical device?

Test cases fall out of the threat model, not out of a library. The twin's components, interfaces, data flows and assets are threat modeled with MITRE EMB3D: component types map to properties, properties map to threats, and ELTON extends both where EMB3D stops. Every threat pins to a component, so test cases generate against exactly that scope.

What are the three verification tiers?

L1 is reachability and control analysis against the digital twin, which removes roughly 30 to 40 percent of findings as Not Affected before anyone touches the device. L2 is static and dynamic analysis of the actual code and firmware, roughly 50 to 65 percent. L3 is on-device exploitation through TestLink, roughly 70 to 85 percent.

Why does deeper access close more findings as Not Affected?

Every tier adds evidentiary weight, and a dismissal is only as strong as the tier that cleared it. L3 is the strongest evidence there is, an executed test case with a pass or fail on real hardware. Deeper access closes more findings and makes every VEX statement stronger, with the chain from CVE to determination unbroken.

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